The present invention relates to a solid-state image sensor, more particularly to a CMOS image sensor that has high resolution, high performance, and very small pixel sizes. In particular this invention relates to a pixel that has only three transistors (3T), two row control lines, and two column control lines. Further more the pixels are still capable of standard low noise correlated double sampling operation, as is typically used with 4T pixel architectures, using low noise p-channel MOS transistors for sensing and resetting without address transistors.
Typical image sensors sense light by converting impinging photons into electrons that are integrated (collected) in sensor pixels. After completion of integration cycle a voltage corresponding to collected charge is supplied to output terminals of the image sensors.
In typical CMOS image sensors the charge is converted to the corresponding voltage directly in the image pixels themselves and the analog pixel voltage is transferred to the output terminals through various pixel addressing and scanning schemes. The analog signal can also be converted on-chip to a digital equivalent before reaching the chip output. Generally, the sensor pixels have incorporated in them a buffer amplifier, typically a source follower, which drives the sense lines connected to the respective sense pixels by suitable addressing transistors.
After charge to voltage conversion is completed and the resulting signal is transferred out from the sense pixels, the sense pixels are reset in order to be ready for accumulation of new charge. In pixels that are using Floating Diffusion (FD) as the charge detection node, a reset transistor is provided for the reset operation. During reset the transistor is turned on, thereby momentarily conductively connecting the FD node to a voltage reference.
Through this step, collected charge is removed from the pixels; however, kTC-reset noise is generated as is well known in the art. The kTC noise has to be removed from the signal by the Correlated Double Sampling (CDS) signal processing technique in order to achieve desired low noise performance. The typical CMOS sensors that utilize the CDS concept need to have four transistors (4T) in the pixel. An example of the 4T pixel circuit can be found in the U.S. Pat. No. 5,881,184 to Guidash.
Since such high performance pixels have 4 transistors incorporated in them the pixels require several signal control lines for their operation. Typically such pixels have a reset line, a charge transfer line, and an address line in the row direction and a supply voltage (Vdd) line and an output voltage (Vout) line in the column direction. It is possible to share some of these line's and corresponding transistors between the neighboring pixels, but this causes other complications related to intra-pixel interconnecting lines. The larger number of transistors and increased number of row and column lines consumes a valuable pixel area and thus significantly reduces the pixel active area that could otherwise be used for charge storage and light sensing. FIG. 1 is a schematic circuit diagram of a conventional 4T CMOS image sensor pixel with a pinned photodiode.
The pinned photodiode 101 is coupled through a charge transfer transistor 102 to a FD node 103. A sensing Source Follower (SF) transistor 104 has its gate connected to the FD node 103, drain connected to a Vdd node 105 and source connected through an addressing transistor 106 to an output column bus 107. The Vdd node 105 is connected to a Vdd column bus 108. The FD node 103 is reset, i.e., connected to the Vdd node 105 by a reset transistor 109. The gate of the reset transistor 109 is controlled by a signal applied on a first row bus line 110, the gate of the address transistor 106 is controlled by a signal applied on a second row bus line 111, and the gate of the charge transfer transistor 102 is controlled by a signal applied on a third row bus line 112.
As photons 113 impinge on the photodiode 101, electron charge is generated there. After completion of charge integration the FD node 103 is reset and all charge from the photodiode 101 is transferred on the FD node 103. This changes the FD voltage from the original reset level to a new signal level. Both levels; the reset level and the signal level on the FD node are then sensed by the sensing SF transistor 104 and both levels are transferred onto the output column bus 107. They are further transferred into column signal processing circuits for subtraction and additional processing. The subtraction of the reset level from the signal level is called Correlated Double Sampling, CDS, which removes the kTC noise and the transistor threshold non-uniformities from the signal to be output. This is one of the main advantages of the 4T pixel circuit.
However, in the 4T pixel circuit, the four transistors occupy a large amount of the valuable active pixel area and three row control lines are required for the operation. This is a disadvantage of this circuit that is some times compensated by sharing the circuits with several photodiodes. However, the circuit sharing has also its disadvantages.
Due to the circuit sharing, the FD node capacitance is increased, which reduces the pixel sensitivity. The interconnection lines need to be additionally provided so they occupy the valuable pixel area. Other disadvantages of this concept are slightly asymmetrical layout and electrical function that result in some asymmetrical optical as well as electrical cross talk problems. It is therefore desirable to maintain the charge transfer concept using the pinned photodiode but reduce the number of transistors in the pixel and to maintain the pixel symmetry.